Silicon Labs /SiM3_NRND /SIM3L167_C /PLL_0 /CONTROL

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Interpret as CONTROL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NOT_SET)LLMTF 0 (NOT_SET)HLMTF 0 (NOT_SET)LCKI 0 (DISABLED)LMTIEN 0 (DISABLED)LCKIEN 0 (ACTIVE_LOW)LCKPOL 0 (RTC0TCLK)REFSEL 0LOCKTH 0 (DISABLED)STALL 0 (DISABLED)DITHEN 0 (FALLING_EDGE)EDGSEL 0 (OFF)OUTMD

EDGSEL=FALLING_EDGE, DITHEN=DISABLED, OUTMD=OFF, STALL=DISABLED, LCKI=NOT_SET, LCKPOL=ACTIVE_LOW, HLMTF=NOT_SET, LMTIEN=DISABLED, LLMTF=NOT_SET, REFSEL=RTC0TCLK, LCKIEN=DISABLED

Description

Module Control

Fields

LLMTF

CAL Saturation (Low) Flag.

0 (NOT_SET): DCO period is not saturated low.

1 (SET): DCO period is saturated low.

HLMTF

CAL Saturation (High) Flag.

0 (NOT_SET): DCO period is not saturated high.

1 (SET): DCO period is saturated high.

LCKI

Phase-Lock and Frequency-Lock Locked Interrupt Flag.

0 (NOT_SET): DCO is disabled or not locked.

1 (SET): DCO is enabled and locked.

LMTIEN

Limit Interrupt Enable.

0 (DISABLED): Saturation (high and low) interrupt disabled.

1 (ENABLED): Saturation (high and low) interrupt enabled.

LCKIEN

Locked Interrupt Enable.

0 (DISABLED): The PLL locking does not cause an interrupt

1 (ENABLED): An interrupt is generated if LCKI matches the state selected by LCKPOL.

LCKPOL

Lock Interrupt Polarity.

0 (ACTIVE_LOW): The lock state PLL interrupt will occur when LCKI is 0.

1 (ACTIVE_HIGH): The lock state PLL interrupt will occur when LCKI is 1.

REFSEL

Reference Clock Selection Control.

0 (RTC0TCLK): PLL reference clock (FREF) is the RTC0 oscillator (RTC0TCLK).

1 (LPOSC0DIV): PLL reference clock (FREF) is the divided Low Power Oscillator (LPOSC0).

2 (EXTOSC0): PLL reference clock (FREF) is the external oscillator output (EXTOSC0).

LOCKTH

Lock Threshold Control.

STALL

DCO Output Updates Stall.

0 (DISABLED): In phase-lock and frequency-lock modes, spectrum spreading, and dithering operate normally, if enabled.

1 (ENABLED): In phase-lock and frequency-lock modes, spectrum spreading, and dithering are prevented from updating the output of the DCO.

DITHEN

Dithering Enable.

0 (DISABLED): Automatic DCO output dithering disabled.

1 (ENABLED): Automatic DCO output dithering enabled.

EDGSEL

Edge Lock Select.

0 (FALLING_EDGE): Lock DCO output frequency to the falling edge of the reference frequency.

1 (RISING_EDGE): Lock DCO output frequency to the rising edge of the reference frequency.

OUTMD

PLL Output Mode.

0 (OFF): DCO output is off.

1 (DCO): DCO output is in Free-Running DCO mode.

2 (FLL): DCO output is in frequency-lock mode (reference source required).

3 (PLL): DCO output is in phase-lock mode (reference source required).

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